Exemplary embodiments relate to a nonvolatile memory device and, more particularly, to a page buffer circuit and a nonvolatile memory device which are capable of storing 3-bit information.
Examples of nonvolatile memory device are random access memory (RAM), which enables the writing and erasure of data and loses data upon entering a power-down down, and read only memory (ROM), which retains data upon entering a power-down mode and thus has recently been widely used for the storage media of portable electronic devices, such as digital cameras, personal digital assistant (PDAs), and MP3 players.
The nonvolatile memory device may include a memory cell array, a row decoder, a page buffer unit, etc. The memory cell array may include a plurality of word lines arranged in rows, a plurality of bit lines arranged in columns, and a plurality of cell strings corresponding to respective bit lines.
Memory cells may have varying threshold voltages according to their program states. Ideally, the memory cells have the same threshold voltage according to the state of data to be stored. However, in practice, when a program operation is performed on the memory cells, the threshold voltages of the memory cells often have a different probability distribution in each region because of various external environments, such as the device characteristics and the coupling effect.
FIG. 1A is a block diagram of a nonvolatile memory device.
Referring to FIG. 1A, the nonvolatile memory device 100 includes a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a voltage supply unit 150, and a control unit 160.
The memory cell array 110 includes memory cells selected on a memory-block by memory block (BK) basis and configured to have data written therein and data read therefrom. The memory cells are coupled to word lines and the bit lines. Any one of the memory blocks BK may be selected and enabled, while the remaining memory blocks BK may be disabled. Furthermore, a plurality of the memory blocks BK may share a bit line.
The page buffer unit 120 includes page buffers coupled to the bit lines. The page buffer is configured to store data to be stored in memory cells coupled to a bit line or to read data stored in memory cells and store the read data.
The Y decoder 130 is configured to provide the page buffers with a data IO path. The X decoder 140 is configured to enable a selected memory block and couple each word line with a line for supplying operating voltages.
The voltage supply unit 150 is configured to generate a high voltage for a program, read, or erase operation, and the control unit 160 is configured to control the operation of the nonvolatile memory device 100 for the program, read, or erase operation.
FIG. 1B is a circuit diagram of a page buffer of the page buffer unit 120 shown in FIG. 1A.
Referring to FIG. 18, the page buffer includes a bit line selection unit 121, a sense unit 122, a precharge unit 123, a latch unit 124, a data sense unit 125, and first and second verification units 126, 127.
The bit line selection unit 121 is configured to select an even bit line BLE and an odd bit line BLO in response to bit line selection signals SELBLE, SELBLO. The sense unit 122 is configured to sense voltage of a selected bit line and to change a voltage level of the sense node SO to the sensed voltage.
The precharge unit 123 is configured to precharge the sense node SO, and the latch unit 124 is configured to receive and store data to be programmed or to store read data. The data sense unit 125 is configured to control the latch unit 124 according to a voltage level of the sense node SO so that data of the latch unit 124 are retained or changed.
The first and second verification units 126, 127 are coupled to a latch node of the latch unit 124 and are configured to output a verification signal indicating whether a program verification operation has been completed.
In such a nonvolatile memory device, with an increase in the number of bits that can be stored per memory cell, the number of threshold voltages used for determining the stored bits and distributions of the threshold voltages among memory cells increase, and the number of times that verification tests for checking whether program operations on memory cells are passes (for example, a pass is a state where a program has been successfully performed) is increased.
Accordingly, a fast verification method for performing a program verification operation using two or more verification voltages through one precharging of a bit line has been developed.
The fast verification method may be performed by precharging a bit line in order to perform a program verification operation and consecutively performing program verification operations while sequentially raising a verification voltage applied to a selected word line.
More specifically, in such a fast verification method, after applying a first verification voltage to the selected word line, a first evaluation operation of a voltage of the bit line is performed. It is then checked whether the bit line voltage has changed. If, as a result of the check, a selected memory cell has a threshold voltage larger than the first verification voltage, the bit line remains in the precharge state.
In response to the determination that the selected memory cell has a threshold voltage larger than the first verification voltage, a second evaluation operation may be performed by applying a second verification voltage larger than the first verification voltage to the selected word line. If, during the second evaluation operation, the bit line remains in the precharge state, the selected memory cell may be determined to have a threshold voltage larger than the second verification voltage.
As described above, a program verification operation using several verification voltages can be performed with one precharging of a bit line. In reference to the structure of the memory cell array 100 of the nonvolatile memory device, unselected memory blocks BK that are also coupled to the precharged bit line are disabled. However, leakage current may be generated through the bit lines coupled to the unselected memory blocks. When an evaluation operation is consecutively performed without precharging a bit line, a concern is raised in that the voltage level of the bit line is gradually decreased due to the bit line leakage current flowing through the unselected memory blocks. Accordingly, in a conventional fast verification method, the number of times in which a program verification operation can be performed through one precharging of a bit line may be limited to two to three times.